Hardware based security and trust.

About Us


Plusquellic Jim LowRes IMG_9225James F. Plusquellic, Ph.D.

President & CEO

Dr. Plusquellic is the founder of Trusted & Secure Systems and is serving as the President and CEO. He has disclosed five inventions, has six pending patent applications. TruSecSys has license agreements with STC.UNM for his hardware security technology. His technology uses a physically unclonable functions (PUFs), which are capable of producing random, but repeatable, bitstrings or keys for applications such as device authentication and encryption.

Professor Plusquellic received both his M.S. and Ph.D. degrees in Computer Science from the University of Pittsburgh in 1995 and 1997, respectively. He is currently a Professor in Electrical and Computer Engineering at the University of New Mexico. His research interests are in the area of nano-scale VLSI and include security and trust in IC hardware, silicon validation, design for manufacturability and delay test methods. Dr. Plusquellic received an “Outstanding Contribution Award” from IEEE Computer Society in 2012 for co-founding and for his contributions to the Symposium on Hardware-Oriented Security and Trust (HOST). He served as General Chair for HOST in 2010, for the Defect-Based Testing Workshop in 2006 and is currently serving as Associate Editor for Transactions on Computers and as Registration Chair for HOST. He received the “10 Years of Continuous Service Award” from the International Test Conference, a Best Paper Award from VTS, an ACM Distinguished Service Award¬†from SIGDA and two Austin CAS Fellow Awards from IBM. He recently received a “2014 Innovation Award” from the Science and Technology Center at the University of New Mexico, is a “Featured Entrepreneur” within the School of Engineering and has 3 patents and several provisional applications filed with the US. Patent and Trademark Office. Professor Plusquellic is serving or has served on the Program Committees for HOST, Design and Test in Europe, International Test Conference, International Conference on Computer-Aided Design and VLSI Test Symposium. He has published more than 70 refereed conference and journal papers. He is a Golden Core Member of the IEEE Computer Society and a member of the IEEE.

Dr. Plusquellic is a leader in the area of hardware security and trust, and is regularly invited by NSF and SRC to participate in professional meeting regarding its future directions.

UNM-Affiliated Pending Patent Applications

  • System and Methods for Generating Unclonable Security Keys in Integrated Circuits
  • System and Methods for Measuring Path Delays in a Circuit
  • System and Methods for Leveraging Resistance Variations in a Circuit and Converting Voltage Drops to Digital Code
  • System and Methods for Leveraging Path Delay Variations in a Circuit and Generating Error-tolerant Bitstrings
  • System and Methods for Analyzing Stability Using Metal Resistance Variations

swarupSwarup Bhunia, Ph.D.

Academic Consultant

Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 150 publications in peer-reviewed journals and premier conferences in the area of VLSI design, CAD and test techniques.

His research interests include low power and robust design, hardware security and protection, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009).

He has served as a guest editor of IEEE Design & Test of Computers (2010), in the editorial board of Journal of Low Power Electronics (JOLPE) and in the technical program committee of Design Automation and Test in Europe (DATE 2006-2010), Hardware Oriented Trust and Security Symposium (HOST 2008-2010), IEEE/IFIP International Conference on VLSI (VLSI SOC 2008), Test Technology Educational Program (TTEP 2006-2008), International Symposium on Low Power Electronics and Design (ISLPED 2007-2008), IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH 2007-2010), IEEE International Conference on VLSI (ISVLSI 2008-2010), International Conference of VLSI Design as a track chair (2010) and in the program committee of International Online Test Symposium (IOLTS 2005).

Dr. Bhunia has given tutorials on low-power and robust design and test in premier conference including International Test Conferences (ITC 2009), VLSI Test Symposium (VTS 2010), and Design Automation and Test in Europe (DATE 2009). He is a senior member of IEEE.

matthew0411Matt Areno, Ph.D.

Chief Technology Officer

Dr. Areno is currently employed as a Principle Cyber Engineer at Raytheon SI-Government Solutions in Austin, TX, where he focuses on mobile security assessment. He obtained his Ph.D. at the University of New Mexico in 2013 while working full-time at Sandia National Laboratories. At SNL, he started working on mobile security projects and served as a liaison to the Trusted Computing Group during the development of the Trusted Platform Module – Mobile specification. Dr. Areno has been published in several conference and journal publications focusing on mobile and embedded security and is currently serving on the technical program committee for the International Conference on Privacy and Security in Mobile Systems. He has 1 patent with SNL for a PUF-based hardware crypto engine, as well as 1 provisional patent for a mobile security framework based on this crypto engine.


Plusquellic Angela IMG_9244Angela Plusquellic, MBA

Chief Marketing Officer

Ms. Plusquellic is a professional writer and communicator with more than a decade of experience in marketing. She developed the marketing plan for the New Mexico Health Information Exchange (HIE) and developed and managed content for the New Mexico Health Information Technology Regional Extension Center (NM HITREC) project. Both projects were funded by the Office of the National Coordinator (ONC) for Health Information Technology. Plusquellic worked for Telligen/IFMC, a quality improvement organization (QIO) and contractor for the Centers for Medicare & Medicaid Services (CMS). She provided strategic planning and leadership for several projects and served as the primary point of contact with the CMS Government Task Leader.


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