Hardware based security and trust.



PUFs leverage electrical variations that results from the imprecisely fabricated features of the wires and transistors on an IC. For example, the resistance of the same transistor varies on each copy of a chip because of manufacturing process variations and represents the source of entropy or randomness that PUFs leverage.

Enrollment refers to the process of generating a secret bitstring for the first time and regeneration refers to the process of regenerating the bitstring again, e.g., after power cycling a cell phone. Ideally, the bitstrings produced during enrollment and regeneration are identical, i.e, there are no errors or bit flips.

This ideal case has never been achieved in a PUF implementation. Although some applications can tolerate bit flips, applications such as cryptographic applications cannot tolerate them, i.e., all regenerations must produce the exact same bitstring and exact reproduction must be achieved across varying environmental conditions, e.g., temperature changes.

But why is error-free regeneration difficult to achieve?

Changes in the resistance of a transistor mentioned above in each copy of the chip can be small, and therefore when two different transistor resistances from the same chip are compared to generate a bit, small changes in the resistance of either transistor introduced by temperature and/or supply voltage variation can easily effect the result of the comparison, introducing a bit flip. The random nature of process variations guarantees that there will always be pairings of transistor resistances that will be similar and therefore, all chips have a high probability that a bit flip will occur.


The non-volatile memory (NVM) PUF 

Most approaches to dealing with bit flips make use of error correction to fix them.

Error correction information is computed during enrollment and stored as helper data in a non-volatile memory, either on- or off-chip. In general, the helper data requirement makes PUFs less attractive commercially because of data management issues, and the possibility that it can be sabotaged by adversaries.

Therefore, a PUF that can guarantee reproducibility of the bitstring without helper data would be a great benefit to the commercialization of PUFs.

We developed the NVM PUF to meet this objective. The source of entropy is the within-die variations that occur in the transistors of the NVM array, with all cells programmed to store a logic ‘0’. Special control signals on the latest commercially available NVMs are used to ‘read out’ the within-die variations of each of the cells to create a Gaussian distribution profile for the entire array. Cells with values in the upper half of the profile are re-programmed to logic ‘1’. The random nature of within-die variations makes the profile, and the corresponding pattern of ‘0’s and ‘1’s, unique for each chip. The reliable storage capability of the NVM itself is leveraged to eliminate the regeneration process and the possibility of bit flip errors.

This approach is applicable on FLASH memory as well as to emerging ReRAM, Spintronic, and NEMS technologies.


For more information about the NVM PUF technology and its benefits, click here.


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